AD6672:IF Receiver_WOSENDONGLI代理AD6672

AD6672: IF Receiver

The AD6672 is an 11-bit intermediate receiver with sampling speeds of up to 250 MSPS. The AD6672 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.The ADC core output is connected internally to a noise shaping requantizer (NSR) block. The device supports two output modes that are selectable via the serial port interface (SPI). With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6672 supports enhanced SNR performance within a limited region of the Nyquist bandwidth while maintaining an 11-bit output resolution. The NSR block is programmed to provide a bandwidth of up to 33% of the sample clock. For example, with a sample clock rate of 250 MSPS, the AD6672 can achieve up to 73.6 dBFS SNR for an 82 MHz bandwidth at 185 MHz fIN.With the NSR block disabled, the ADC data is provided directly to the output with an output resolution of 11 bits. The AD6672 can achieve up to 66.6 dBFS SNR for the entire Nyquist bandwidth when operated in this mode.

AD6672 特性

Performance with NSR enabled
SNR: 75.2 dBFS in a 55 MHz band to 185 MHz at 250 MSPS
SNR: 72.8 dBFS in an 82 MHz band to 185 MHz at 250 MSPS
Performance with NSR disabled
SNR: 66.4 dBFS up to 185 MHz at 250 MSPS
SFDR: 87 dBc up to 185 MHz at 250 MSPS
Total power consumption:
358 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p
(1.75 V p-p nominal)
Differential analog inputs with 350 MHz bandwidth
Serial port control
Energy saving power-down modes
User-configurable, built-in self test (BIST) capability

AD6672 建议配套产品

推荐AD6672使用的驱动放大器

针对差分RF/IF，推荐使用超低失真 ADL5562。

针对直流耦合输入，推荐使用 ADA4927-1或ADA4938-1。

推荐AD6672使用的IF数字可变增益放大器

针对数字通信系统中的全差分输入和输出DVGA，推荐使用ADL5202或AD8376。

推荐AD6672使用的时钟驱动器

如需低抖动性能，推荐使用AD9510、 AD9511、 AD9512、 AD9513、 AD9514、 AD9515、或AD9516、 AD9517 系列多路输出时钟之一。

如需低抖动性能和集成VCO，推荐使用AD9520或AD9522、AD9522系列可选VCO频率器件之一。

如需低抖动性能及片内集成PLL和VCO，推荐使用AD9523、 AD9523-1或AD9524。

推荐电源解决方案

欲选择电压调节器产品，请使用ADIsimPower。

欲选择电源监控器产品，请使用电源监控器参数搜索。

AD6672 技术指标

Resolution (Bits): 11bit
# Chan: 1
Sample Rate: 250MSPS
Interface: LVDS
Analog Input Type: Diff-Uni
Ain Range: 1.75 V p-p
ADC Architecture: Pipelined
Pkg Type: CSP

AD6672 芯片订购指

产品型号	封装	引脚	温度范围	包装和数量	报价*(100-499)	报价*1000 pcs
AD6672BCPZ-250 产品状态: 量产	LFCSP:LEADFRM CHIP SCALE	32	工业	Tray, 490	$ 52.00	$ 44.20
AD6672BCPZRL7-250 产品状态: 量产	LFCSP:LEADFRM CHIP SCALE	32	工业	Reel, 1500	$ 52.00	$ 44.20